量子电路是在量子器件, 上实现量子算法的核心，其中量子门必须是可逆的。许多量子算法依赖于布尔函数,，因此必须在量子电路中可逆地实现。可逆电路综合提供了一种将此类布尔函数转换为可逆电路的方法。二元决策图(BDDs) 提供了一种可扩展的方法来完成此任务,，但生成的 BDD 和电路在很大程度上取决于变量排序。现有的排序启发法通常会最小化 BDD 大小，因为它与电路大小密切相关。然而，, BDD 大小并不能完美地代表合成电路 (QCC) 的量子成本。我们提出 \texttt{QuantumEvo}, 一个进化框架，该框架使用 LLM 作为 QCC 感知 BDD 变量排序的启发式生成器。不是直接预测排序, \texttt{QuantumEvo} 对从多个启发式系列初始化的排序启发式进行搜索。候选启发式使用标准 BDD 操作直接操纵变量排序，并由下游 QCC 选择。所发现的启发式, HGA-QE, 修改了遗传算法内的筛选步骤，以便该过程更好地与 QCC 保持一致。在基准设置中，, HGA-QE 相对于每个函数的最佳基准实现了 70.9\% 的平局或获胜率，并且在 13.5\% 的函数上绝对是最佳的。结果表明，QCC 性能具有广泛的竞争力,，而 HGA-QE 在严格获胜的两个基准套件中显示出更明显的相对优势，这两个基准套件的来源不同于启发式发现所用的数据。

Quantum circuits are central to implementing quantum algorithms on quantum devices, where quantum gates must be reversible. Many quantum algorithms rely on Boolean functions, which must therefore be implemented reversibly within quantum circuits. Reversible circuit synthesis provides a way to translate such Boolean functions into reversible circuits. Binary decision diagrams (BDDs) offer a scalable approach to this task, but the resulting BDDs and circuits depend heavily on variable ordering. Existing ordering heuristics commonly minimize BDD size because it is closely tied to the circuit size. However, BDD size is an imperfect proxy for the quantum cost of the synthesized circuit (QCC). We propose \texttt{QuantumEvo}, an evolutionary framework that uses an LLM as a heuristic generator for QCC-aware BDD variable ordering. Instead of predicting orderings directly, \texttt{QuantumEvo} searches over ordering heuristics initialized from multiple heuristic families. Candidate heuristics directly manipulate variable orderings using standard BDD operations and are selected by downstream QCC. The discovered heuristic, HGA-QE, modifies the sifting step inside a genetic algorithm so that the procedure is better aligned with QCC. Across the benchmark set, HGA-QE achieves a 70.9\% tie-or-win rate against the per-function best baseline and is strictly best on 13.5\% of the functions. The results demonstrate broadly competitive QCC performance, with HGA-QE showing a clearer relative advantage in strict wins on the two benchmark suites drawn from sources different from the data used for heuristic discovery.

科目: 人工智能 (cs.AI); 硬件架构 (cs.AR)

Subjects: Artificial Intelligence (cs.AI); Hardware Architecture (cs.AR)